In computer systems, which are used to bridge multiple data processing networks, the movement of data between the networks is performed by the CPU (Central Processing Unit) of the system which bridges one network to another. The speed of the transfer from one network to another is governed by the speed of the CPU. In the case of large amounts of data being transferred, the CPU will pose the limiting factor on the transfer throughput.
In these computer systems, direct memory access (DMA) or cycle stealing is used to off-load the task of moving data between computers, I/O (input-output) devices and the computer memory subsystem from the CPU. By using the computer's system bus, when it is not being used by the CPU, the DMA can increase the overall data throughput of the computer system. Memory accesses of the system are then shared between the CPU and the I/O devices. Even this DMA architecture has limitations as it too relies on the same single system bus for access to the memory subsystem. The contention between the CPU and the DMA for system resources still exists and limits the throughput of the system, and thus of any networks bridged by the computer system.
For example, in a 80186 CPU system clocked at 20 megahertz and supporting peripherals including a 10 Mbps (megabytes per second) Ethernet Controller and a 4 Mbps per second IR controller, when the Ethernet Controller and the IR controllers are both in operation, memory accesses are required every 570 nanoseconds. With the 80186 CPU clocked at 20 megahertz, the DMA must have access to the memory subsystem once every 3 CPU cycles. This is a 30% reduction in performance of the CPU and results in the I/O data rate quickly overrunning the system. Therefore, conventional DMA implementation is inadequate to provide the performance which is need in this example.